1. Field of the Invention
The present invention relates to a non-volatile memory device, and more particularly, to an electrically erasable programmable read-only memory (EEPROM) having improved programming and erasing characteristics and a method of fabricating same.
2. Description of the Related Art
A non-volatile memory device is a device in which data is not erased even if a supply of power is discontinued. EEPROM is a type of read-only memory (“ROM”) that is non-volatile and electrically erasable and programmable. In general, data in the cells of an EEPROM can be erased upon localized application of an electric field to each cell. The basic structure of an EEPROM cell may include an oxide layer sandwiched between two transistors. The two transistors are known as a control gate and a floating gate, respectively.
As the integration density of semiconductor memory devices increases, smaller floating gates must be used. However, a high voltage is needed to program a non-volatile memory or erase data from the non-volatile memory, and the smaller floating gates make it difficult to maintain boundaries when defining a tunnel. Thus, reducing the size of a floating gate makes it almost impossible to program or erase data from an EEPROM. For this reason, non-volatile memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS), ferro-electric random-access memory (FeRAM), single-electron transistor (SET), and non-volatile read-only memory (NROM) devices, which are substitutes for the floating gate type cell, have been developed. In particular, much attention is being focused on the SONOS cell as a next-generation cell that can replace the floating gate type cell.
A typical SONOS EEPROM is shown in FIG. 1. Referring to FIG. 1, an oxide-nitride-oxide (ONO) layer 47 and a control gate 50 are formed on a substrate 1. The ONO layer 47 is a stacked structure of a lower oxide layer 10, a nitride layer 40, and an upper oxide layer 45. A source junction region 90 and a drain junction region 95 are formed in the substrate 1 at opposite sides of the ONO layer 47.
The lower oxide layer 10 is a tunneling layer. The nitride layer 40 is a memory (storage) layer that stores an electric charge or discharges the electric charge from a trap site so as to control a threshold voltage of a cell. That is, the nitride layer 40 acts as a memory unit. The upper oxide layer 45 is a blocking layer that prevents an electric charge from escaping the ONO layer 47.
A non-volatile memory is programmed using Fowler-Nordheim tunneling (F-N tunneling) or channel hot electron (CHE) injection, whereby electrons, for example, collect in the ONO layer 47. In general, CHE injection is preferred to F-N tunneling, which requires a high voltage.
In a conventional SONOS EEPROM in which the ONO layer 47 formed below the control gate 50 has a flat-stacked structure, either voltage applied to the control gate 50 must be increased or the ONO layer 47 must be thinned in order to enhance programming efficiency. However, thinning of the ONO layer 47 decreases charge retention, thereby lowering reliability.
In an effort to address the problems of the conventional SONOS cell, U.S. Pat. No. 5,768,192 to Eitan relates to programming and reading operations performed on a non-volatile semiconductor memory device in asymmetrical ways. That is, if a non-volatile semiconductor memory device is programmed using CHE injection, electrons are stored only in regions adjacent to drain regions. A difference in threshold voltage between locally charged regions is measured to distinguish between cells having a value of “0” (i.e., a programmed state wherein electric charge is prevented from passing to the control gate) and cells having a value of “1” (i.e., a blank state wherein electric charge is able to pass to the control gate. A lateral electric field generated when a voltage is applied to a source region of a nitride layer, i.e., a region that is not charged with electrons, is weaker than a lateral electric field generated when a voltage is applied to a drain region of the nitride layer. Therefore, it is possible to obtain a better cell window (i.e., an opening allowing electrical connection between layers) by applying a voltage to the source region of the nitride layer. However, if the size of a cell, i.e., channel length or distance between the source and drain, is smaller than a predetermined size, problems such as punch through or junction breakdown are caused when a voltage is applied to the cell via a thick ONO layer during CHE injection. In this case, it is impossible to perform ion implantation around the cell. However, a problem exists in that because an electron storage region is wider, the operation of a conventional non-volatile semiconductor memory device depends largely on the length of a nitride layer. Further, the range of a hole filling region is limited to an area around a junction region.